QUALITY AND INTEGRITY
To ensure that our solutions and other research and development activities meet the most exacting standards regarding quality control, responsible behaviour and ethics,
Explore The SCIHUBSS
Significant advancements are currently transforming semiconductor chip design, with engineers developing VLSI systems that are increasingly autonomous and capable. These breakthroughs are no longer the result of isolated genius but rather the product of effective, collaborative efforts. SCIHUBSS brings together a network of partners, leveraging shared talent and infrastructure to foster these collaborative synergies and drive innovation forward.”
WHO WE ARE
We are a dedicated team committed to upholding industry standards and delivering excellence through collaborative efforts to meet our customers’ needs. Our team combines expertise from leading semiconductor design firms, bringing a deep understanding of semiconductor design and verification processes, methodologies, and technologies. With our collective knowledge and experience, we ensure top-notch solutions tailored to your specific requirements.
key SKILLS
PD (Physical Design): The SCIHUBSS expert Team will provide support throughout RTL to GDSII stages of ASIC design flow. Our team has extensive experience in advanced flows for power aware synthesis (UPF, CPF), timing constraint generation (STA), netlist floor planning for the best possible PPA and place and route(PNR) for overcoming ever-increasing complexity. Our engineer’s in-depth knowledge of EDA tools and scripting skills enable us to deliver full turn-key ASIC development.
STA/Synthesis : The SCIHUBSS is one of the most important areas in Semiconductor chip design. Having in-depth knowledge and exposure in STA provides an opportunity to explore and understand how other domains operate to design chips. As experts say Timing and Performance is almost everything, STA is the single most important domain that collaborates with every other area of chip designing. Scihubs’s team can help meet customer requirements and deliver as per expectations.
PV (Physical Verification): The SCIHUBSS verification team has proven expertise on taking complete ownership of verification. Verification is one of the key issues in IC design and development impacting product schedules and timelines. We offer a wide range of ASIC verification services to help customers, especially physical verification checks like DRC, LVS, ERC, DFM, ESD, Antenna.
Analog Layout/Design: The SCIHUBSS Layout team has extensive experience in high speed and core analog layout. Our team has in-depth expertise on variety of IPs such as SerDes (10, 16, 30 & 56 Gbps), DDRphy, USB 2.0, MIPIphy and Power management. We have also handled expanded portfolios of Data converters, clock circuits such as PLL, DLL & oscillators, Regulators, Bias, Bandgap references, Temperature sensors, UVLOs etc Scihubs’s Team has proven experience on different process nodes to the cutting edge technology: Planar (180nm, 130nm, 110nm, 65nm, 55nm, 45nm, 40nm, 32nm, 28nm, 20nm and more) and Finfet (16nm/14nm, 12nm, 10nm, 7nm, 6nm, 5nm) with foundry TSMC, Samsung, UMC, GF and Intel. Multiple full chip and IP level tape out has been successfully done with first pass silicon.
Design Verification: The SCIHUBSS has one of the industry’s strongest teams in design verification. Our team can execute verification from scratch of complex SoCs and IP’s by using latest methodologies such as SV-UVM, UPF and meeting key KPI such as 100% functional and code coverage Advanced IP & SoC Verification. We also provide silicon proven VIP for latest IP’s and provide source code and aftersales support to our customers.
DFT: The SCIHUBSS has one of the industry’s strongest teams Digital Design and Semiconductor Technologies. In-Depth knowledge in terms of DFT Methodologies, such as scan based testing , ATPG (Automatic Test Patter Generation ), and BIST , is also crucial.
RTL: : The SCIHUBSS A solid foundation in these areas is important. HDLs: RTL design engineers need to master the syntax and semantics of HDLs. RTL simulation, synthesis, and verification: RTL design engineers need to know the tools and methods for these tasks.Architecture: A deep understanding of ARM Micro Architecture is helpful. Computer architecture and FPGA.
OUR CLIENTS
