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PD FLOW Short Notes 

Inputs file and contains

  • Libraries
  • Tech-File (.tf à Synopsys, tech-lef Cadence )
    • it contains all the technology related parameters )
    • Unit tile info
      • Unit tile height (site row height )
      • Unit width (placement Grid–Fill X1 size)
    • Metal layer details
      • Min-Width
      • Min-Spacing
      • Metal Pitch
      • Fat Metal Spacing Table
    • VIA Layer Details
      • Min-space
      • Single –cut via
      • Double –Cut Via
    • TLU + ( tlu+ Synopsys ,Captbl or qrc tech Cadence )
      • R & C Values for each metal & via Layer in sq micron
        1. Moderate accurate
        2. Deferent from each corner
      • CBEST/CWORST/RCWORST/RCBEST/TYPICAL
    • Logical /Timing /power library (.lib or .db)
      • It contains following details
        1. Timing (in the form of 7X& table)
      • Cell –Rise-delay
      • Cell-,fall delay
      • Output rise transition
      • Output fall transition
      • Setup/hold timing requirement
        • Power (in the form of 7X7 table)
      • Leakage power
      • Internal power
        • Area (Cell Area )à all and gates and OR gates …etc
      • Types
        • CCS library (More accurate, 2% correlation to actual spice simulation  )
        • NLDM Library ( less accurate 7% correlation to actual spice simulation ) above28and below we use CCS library
  • Physical Library ( .lef or FRAME or NDM model)

  It contains the following Physical Parameter details

  • Cell size (width x height )
  • Allowed Orientation
    • RO, R180,MX,MY etc
    • If you want you can flip 90,270 not allowed
    • 180,360 degrees is allowed
  • Cell class
    • CORE –Standard Cell
    • BLOCK-Macros
    • PAD – IO Pads
  • PIN Details
    • Layer Details
    • A,B,Z àPin details
    • Direction
    • Location
  • Obstruction /Routing Blockage Details
  • Different Types
    • LEF – Library Exchange Format (used in Cadence & Siemens/AtopTech Tools)
    • FRAM – FRAME View (used in Synopsys IC-Compiler)
    • NDM –New Data Model (used in Synopsys IC-Compiler 2 & fusion Compiler )

Netlist (Gate level)

  • Design functionality in Verilog gate level netlist format

SDC (Synopsys design constraints –timing constraints)

Clock definition

create_clock

create_generated_clock

Clock Attributes

Set_clock_latency (Not useful for PD engineers,but used during synthesis)

Set_clock_uncertanity

Set_clock_group

Set_sense

Set_clock_transition

Set_min_pulse_width

Group_path

DRV Constraints

                Set_max_transition

                Set_max_capacitance

                Set_max_fanout

Constant definition

                Set_case_analysis

Path exceptions

                Set_multicycle_path

                Set_false_path

                Set_disable_timing

Max/Min Delay

                Set_max_delay

                Set_min_delay

I/O Delay Definitions

                Set_input_delay

                Set_output_delay

                Set_load

Set_input_transition

Set_driving_cell

Push-Down-Floorplan –DEF /TCL (Block Shape & IO ports Placement & PG Routing Push-down)

FP DEF –read it using “read_def or defin” command

TCL file –just source it inside the tool shell.

.fb-read it using “read_floorplan ” cmd

UPF-United Power Format (if the design contains low power methodologies)

  • PG Net Details
  • PG logical connection (connect pg or globalNetConnection àcadence)
  • Power Domain Details
  • Multi-supply (0.8V &1.3V)
  • ON/OFF (using power- switches)

Level –shifters

Isolation Cell Policies

PST-Power state Table

Scan-DEF (Needed for Scan-chain re-order)

                Scan-chain Details

                Registers belonging to particular scan-chain

Link Library (Timing lib for all the cells used in the design)

  • RTL/Gate-Level Netlist may contain hand instantiated std cells and macro .
  • You need to read them inside tool, so that the tool understands s the timing /logical/power info.

Target library: (Timing lib -Optimization engine will pick use the cells from these libs)

  • during the Opt, the tool would use the cells from these target lib

Sanity checks

  • netlist check (cmd: check_design or check_netlist )
    • no floating inputs or nets
    • no multi –driven nets
    • no black –box or empty modules
    • output connected to P/G
    • No Combinational feedback Loops
    • No assign statement
      • Net a
      • Assign net b=a
  • SDC Checks (cmd ; check_timing )
    • Register driven by multiple clock
    • Un-constrained end points
    • Missing clock definitions
    • Missing IO Delays
    • Combinational Loops
  • Library Check (cmd :check library ) (not applicable for IIC2 & Fusion Compiler )
    • Check if there is any physical or timing model is missing for the cells.
    • Library consistency check (PIN direction should be same across LEF & LIB)
  • Zero wire Load Model Timing Check (Netlist Vs SDC Check )à
    • Cmd :set_zero_interconnect_delay_model_true
    • Cmd report_qor
    • Cmd:report_timing
    • Make sure your design is meeting setup with zero wire-delay.
  • Netlist Vs Floorplan Checks (cmd:check_pin_placement )àtop level guy  and block level designer there are not be in shink we need to check  Netlist Vs Floorplan
    • All the I/O ports should’ve assigned physical location
    • No I/O ports short.
    • No I/O ports near the corners (causes congestion & Routing issues )

Floorplan           

  • Goal
    • Minimize the Die-Size/Area
    • Avoid the dead area /avoid the spaces
    • Minimize the congestion
    • Minimize the timing violation
    • Reduce the wire length
    • Making routing easy
    • Reduce the IR drop better PG routing
  • Floor plan shape initialization
    • Read the push-down FP or manually initialize the shape.
    • Read Def. or DefIn (DEF format )
    • Source (TCL File )
    • Read Floor plan or Read plan (.fp)
    • Manually initialize the shape & place the IO ports (bottom –up approach )
  • Macro Placement
    • Group the macro based on hierarchy module
    • Fly-line based connectivity analysis
    • Data-flow diagram.
    • Guidelines
      • Place the macro around the core/periphery.
        • High priority: where no IO ports present.
        • Make sure to place the macros where less no of I/O  ports present
        • Provide more space for routing if more I/O ports are present.
        • Don’t place any macro in the middle as it might cause congestion issue.
        • Place the macros in middle only if the macro is timing critical.
          • Add partial (allowed only 30%) blockage to avoid congestion around the macro

Placement Blockage

  • Add placement blockage wherever needed/applicable
    • Soft blockages in macro channels
    • Partial blockages in notch area
    • Hard blockages if any area need to be keep empty

Perform PG routing

  • Enable PG logical connection (connect pg ,global Net connect  )
  • PG Nets – to be routed
  • No of stripes
  • Stripe width
  • Stripe pitch
  • Follow pin/std cell rail creation
  • PG VIA Addition àhelp in lesser IR Drop
    • No pg opens and shorts

Floor plan checks

  • No macro overlaps
  • Macro placed on placement grid
  • No I/O port short
  • I/O port should be present on routing track
  • Clock IO Port double width and Double Spacing
  • All the macro and I/O ports should have fixed attribute
  • No blocked port/pin
  • Enough channel between Macros
  • At least 1 VDD & VSS stripe should be present in the macro channel.
  • No PG nets Shorts & opens.
  • Commands
    • Check_pin_assignement
    • Check_legality
    • Check_pg_drc
    • Check_pg_mising_vias
    • Check_pg_connectivity
    • Check_lvs –nets {VDD VSS}

Note: QUALCOMM PNR à1 week FP Exit à finalizes the DB floor plan DB

Fp freeze àplace freeze àCTS freeze à route freeze

After floor plan à 2 weeks timing for place cts and route

                                PRO Exit /Route Exit /Route Freeze

Floor plan db release into central Area

Really have the problem go and redo the steps

Pre-Place

Goal

  • Adding the physical cells & placing the critical logic cells
  • End Cap (avoiding the damage near edges & helps in having a clean NW at the boundaries )
  • TAP-Cells (Avoids the Latch-up Violation )
    • Bulk –connection for –NMOSàlatch up finamina  won’t happen
    • Well-tap connection for –PMOS àlatch up finamina  won’t happen
    • Tape cells added regular interval distance based on the technology  20micron meter  
  • I/O or Boundary buffer/ interface buffer (improves the I/O signal transition )àwith in 25u we need place
  • De-cap à reduce the dynamic IR drop used for dynamic power àleakage is there bad for static IR drop
    • To many de-caps not good for static power
    • Where we have hot sport is there we need to add the de-cap cells
    • IP vender provide the details add the de-caps
  • Spare cells (will be used for ECO roll in during re-spin)
    • Every 100 x 100 or 80 x 80 we have in the design we need add the post tape out stage
    • Save your money
    • Mask preparation àmanufacturing
    • Metal only Eco open 2 or 3 layer we can fix the bug
    • Total 80+Layers makes are there we will touch 4 or 5 layers we touch
    • Reducing the mask preparation cost & time
    • 6month à5 month take for spare cells
  • What is physical cells?
    • Endcapàsite the where row start and row ends avoid the cell damages near the cells
    • Tap decapà use avoide the latch up problem

Cmos Bulk ,cmos twin-tube , Cmos SOI (silicon on insulator )

We use cmos Bulk

  • Filler
  • Tie-cells

 

Std Cell Placement

  • Goal
    • Place all the std cells inside core area.
    • Meet the timing requirements.
    • Reduce the std cell utilization
    • Reduce the routing congestion
    • Minimal cell density ,pin density and congestion hot-spots
    • Reduce the wire-length (global routing Wires )
    • Reduce the power
  • Std Cell Placement
    • Process of placing the unplaced standard cells in the core area
    • The tool determines the location for all the cells based on the macro placement
    • Timing is high priority during the placement.
    • Tool analyses the timing and optimizes the violation paths
    • Tool analyses the reducing congestion based on global routing and optimizers it.
    • Area recovery on the paths that are having a huge positive setup slack
  • Types of placement
    • Timing driven (timing will be the high priority ,congestion will be the medium priority )
    • congestion driven (timing will be the medium priority ,congestion will be the high priority )
    • Power driven (power will be the high priority ,other will be the medium priority )
    • Timing driven (timing will be the high priority ,congestion will be the medium priority )
    • Area driven (area will be the high priority ,other will be the medium priority )
  • Inputs/Checks
    • Floor plan completed DB
    • Fixed attribute for all the IO ports, Hard macros and pre-placed cells.
    • Critical path groups if any
      • Group_path –from <start-point> -to <end-point> -weight 10
    • Placement Blockages (Add missing blockages & remove if any blockages is unwanted)
    • Scan-DEF (scan-chain info, required for scan chain info ,required for scan-chain re-ordering )
    • Bounds, regions & Groups (Guide the tool to place the cells in the given area )
    • Local cell density limits (Max 90% local density )
    • Keep-out of the cell padding (applied on complex cells like OAI & AOI to reduce the congestion)
    • Apply the don’t use cell list & dn’t touch list.
      • LIB: 350 hvt, 350 rvT 350 lvt TOTAL =1050 DON’T USE THE CELLS
      • X32 CELSS we block high EM this is the reason
      • How to put the cells in don’t use cell ,put in your design scripts like don’t use cell list
    • Make sure to follow IP integration guidelines if any
  • Placement Steps
    • Global placement (seed for the details placement )
      • Divides the design into smaller bin
        • Smaller GRC (global routing cell )bin 5rows height
      • Places the std cells inside each bin & cells are approximately placed i.e GRC
      • Cells are placed module-wise based on the macro placement
      • Std cells may or may not legalized.
      • Timing is not analysed
    • Detail Placement ( Multiple iteration tll the goals are meet )
      • Legalize the cells
      • Timing Opt
      • DRV Opt
        • DATA TRAN FIXES:
        • Size_cell
        • Cmd: split_fanout -driver {/Z} -loads {/I, /I, /I} -lib_cell BUFFD4BWP210H651CNODLVTLL
      • Congestion Opt
      • Tie-Cell addition
      • Scan chain re-ordering
      • HFNS (high Fan-out Net Synthesis  (scan enable ,reset nets are called HFNS )
    • Timing optimization at placement stage
      • In most of the design approximately 30% of the paths will be timing critical
        • 100% have timing critical you need to look on the design
      • Timing driven placement with high effort
      • Incremental timing optimization
      • Allowing LVT cells for Optimization. (5% of LVT cells )
      • Creating path group for critical paths & apply more weightage.
      • Enable the useful-skew while performing timing optimization
        • CCD –ICC2/FC , useful-skew à Innovus
      • Bounds/Region/Groups, so that the tool would place the cells in given location
      • Pre-place the critical logic cells & guide the tool.
      • Use magnet placement to pull the cells closer
      • Routing layer promotion for critical nets
    • Congestion Analysis
      • Report the global-route based congestion
        • Supply vs demand
      • Check the congestion numbers in the report.
      • Visually check the congestion map
      • Visually check the Cell-Density Map
      • Visually check the Pin-Density Map.
      • Check for wrong macro placement/orientation.
      • Check for any blocked port/pins.
      • If I/O port of BUS are not grouped, can cause congestion.
      • Dense PG Network.
        • PG resource usage it should be always <25%
        • More than that get the trouble
  • Check the complex cell (?) ratio in the design
    • Total 1 M cells in my deign
    • 47% complex cells design is not closed
    • Complex cells =>35%
      • AOI, IOA, OAI
      • More than 35-40% we need to take care
      • Too much congestion for complex cells we need to care
  • Check The allow the metal layer for routing, wrong setting can cause congestion.
  • Congestion Fixes
    • Perform congestion-aware placement ,perform area Recovery
    • Add partial placement blockage to control the cell density.
    • Add soft placement Blockage in Macro channels
    • Add cell padding to the cells which is causing the congestion
    • Enable the Scan-Chain reordering.
    • Understand and Use-the all congestion related switches in the tool
    • Add route guides to guide the routing.
    • Update the global Route after timing fixes –it could have reduced congestion tool
  • QoR /Quality Check
    • Zero unplaced cells
    • No cell Overlaps
    • All the cells should be legally placed (on placement grid and row )
    • Timing QoR
      • DRV (Max Tran, Max Cap & Max Fan-out )
      • Setup
      • No Hold check (clock is ideal & skew is zero. Won’t check hold when clock is ideal )
    • Congestion should be under control
      • Congestion report (report congestion)
        • Both H& V should be <0.5%
        • Max Overflow should be <4
        • Check congestion value for each layer if the design is congested.
      • Congestion Map (Highlight & Visually check )
      • Cell –Density Map (Highlight & Visually check )
      • Pin-Density Map (Highlight & Visually check )
    • Cell Utilization growth.
      • Growth should not be more than 5% to 7%.
    • Check the Vt % (make sure ULVT/LVT are used less )

 

 Placement Stage Commands

    •   Place_opt # stage the constitute the default flow for the place_opt command
      • 5 stages
        • Initial_place
        • Initial_drc
        • Initial_opto
        • Final_place
        • Final_opto
      • Create_placement # to perform coarse/global placement only
      • Magnet_placement # to pull the cells closer , so that the timing will be met
      • Legalized_placement # to perform the legalization
      • Refine_placement #increment opt :refine the placement and minimize congestion
      • Report_utilization ( to report the utilization )
      • Check_leglity –verbose # check the placement legality
      • Report_placement
      • Group_path –name critical_1 –from regA/CLk –to regB/D –weight 5
        • Create a group path most violated in the design
      • Create_keepout_margin –type hard –outer {0.15 0 0.152 0} [get_lib_cells */*OA*]
      • Create_bound –name x –coordinates {0 0 10 10 } [get_cells –hier xyz] (Bound/Group)
      • Report_qor (Timing & Area Summary)
      • Report _global_timing (Setup & Hold Summary )
      • Report_timing (Detailed timing report )
      • Report_constraint –all violations (DRV Violation + other like setup and Hold ..etc )
      • Report_congestion (to report congestion)

CTS

  • Goals
    • Reduce the insertion delay
    • Meet the skew targets
    • Reduce the clock cell count
    • Reduce the clock-tree power
      • Compare to data path clock switches twice
      • Data path : approximately switches one time for 5 clock cycles
      • Switching activity 0.2
    • Reduce the OCV violation
      • Increasing the common path CPPR/CRPR come into the picture
      • Common path have less OCV impact ,moe the common path OCV variation are higher
    • Inputs
      • Insertion Delay target
        • Insertion delay =network ID only
        • Latency = source latency + network latency
      • Skew target (Global Skew )
        • Skew = capture clock – launch clock
      • Clock Cells (Like CKBUF or CKINV)
      • Clock routing layer (Always top 2 Metal layers after PG routing )
      • NDR (Double width and Double Spacing )
        • Root level NDR
        • Leaf-level NDR
      • Clock-transition (10% of clock speed )
        • Root level transition
        • Leaf level transition
      • Clock tree exceptions
        • Float-pin (custom insertion delay setting for the sink )
        • Exclude-pin (Exclude the sink pins from skew balancing )
        • Through –pin ( treat the sink pin as not an endpoint )
        • Stop pin (treat combo cell pins as sink pin )
      • Inter-clock balancing if any
  • Flow
  • Types of Clock – tree
    • Traditional clock tree (load Balancing )
      • High insertion delay due to more logic level in clock path & high skew.
    • H-Tree
      • Moderate insertion Delay & less Skew.
    • Clock-Mesh
      • Less insertion delay & less skew.
    • Multi-Point CTS
      • Less insertion Delay & Moderate Skew.
    • Fish-Bone
      • Moderate Insertion delay & Moderate Skew
    • Checks
      • Insertion Delay
      • Skew
      • Clock-cell count
      • Clock –DRV
      • Clock-cell area
      • Std Cell utilization
      • Timing QoR
        • Clock & Data DRV (Max Tran, Max Cap & Max fan-out )
        • Setup & Hold (we should check for hold since the clock is propagation)
        • Min-pulse width Violation
      • Congestion should be under control
        • Congestion report (report congestion )
          • Both H & V Should be < 1%.
          • Max overflow should be < 5
          • Check congestion value for each layer if the design is congested
        • Congestion Map (highlight & visually check)
        • Cell-Density Map (Highlight & Visually check )
        • Pin-Density Map (Highlight & Visually check)
      • Std Cell Utilization growth.
        • Growth should not be more Then  2% to 3%
      • Commands
        • check_clock_tree (Check For Postential Issues Which Can Harm The CTS )
        • check_physical_design –stage pre_clock_opt (check if the design is ready for CTS )
        • define_routing_rule (create NDR rule which will used while performing CTS)
      • Routing
        • Establishing the actual wiring (or metal connection ) using available metal layers
        • Pre requirement :
          • All cells should be legal placed
          • No cell overlaps
          • Make sure CTS is done
          • Timing DRV ,setup & Hold should be clean
          • Congestion number should be control
          • Identified the allowed layer for routing (example min layer m2,max layer –m9)
          • Antenna setting
          • SI /Cross-talk setting
        • Order for Routing
          • Special routing /pg routing
          • Clock routing
          • Regular signal routing
            • Timing critical net first
            • Rest others next
          • Types of routing
            • Global routing
              • Area is divided into smaller bins (GRC)
              • It identifies the available tracks in each bin
              • Assign the tracks & layers for nets
              • Won’t add any via’s
            • Details Routing
              • Add VIAs and completes the net connection without worrying about DRC
              • Check for opens and shorts clear the same if found any 
              • Search for DRC Violation and repair using different routing topology like
                • Detour the net
                • Change the layer
                • Change the VIA type
              • Redundant Via addition
                • Where ever we have space we need add the Redundant via for yield improvement
              • Checks
                • Opens and shorts
                • Physical DRC violation
                • Timing QoR
                  • Clock & data DRV (Max Tran ,Max Cap & max fan-out )
                  • Setup & Hold
                  • Min-pulse width violation
                • Commands
                  •  

RC Extraction

 Inputs

  • Design (DEF/GDS/OAS/NDM)
  • Tech-file (nxtgrd if Star-RC)
    • C-Worst
    • C-Best
    • RC Worst
    • RC Best
    • C-Typical
  • LEF file for all the (Std Cells & Macros)
  • Mapping File
    • Use when streaming out the GDS
  • Temperature ex: -40 to 125C
  • Format :SPEF

Coupling Cap writes out or not: Yes/No

  • What happen if I don’t add metal files
    • Density violations is not clean
    • Because each layer min 50% and max 70%
  • Without filer never go for Physical Verification check
    • Latch-up …etc
  • Metal fill timing is degrading – distance between cap is less
  • Without metal fill looks like timing is clean — distance between cap is high
  • Two more iteration to fix those violation

SPEF Content:

  • Header Section
  • Name-MAP
  • NET Section
    • Connection
    • Capacitance
    • RESISTANCE

Output

  • Summary à RC is in completed
  • Summary à RC is completed

STA

Inputs :

  1. Timing Libraries (.db formate )
  2. Design Netlist (from Route DB)
  3. SDC
  4. SPEF
  5. OCV/AOCV/POCV Settings –40nm and bellow it will come into the picture

Flow

  1. Read Timing libraries (.db formate )
  2. Read Design Netlist (from Route DB ) à
  3. Link the design
  4. Read the SDC
  5. Check_timing à any reg without any clock ,IO delay ,set driving ,set_load ,set case analysis 0 or 1 …etc
  6. Read SPEF
  7. Report_annotated_parasitics à10,000 nets
  8. Apply OCV/AOCV/POCV setting if any àtiming derate
  9. Perform update_timing
  10. Save_session
  11. Write out all the required reports
    • Qor
    • Constraints
    • Setup
    • Hold

 

Physical verification

DRC  design rule check  

LVS – layout vs schematic

ERC – electrical rule check

ANT – antenna

BUMP –

BOUNDARY —

DRC

INPUTS FOR CALIBER DRC

  1. Full GDS (with OD_PO & metal fills added )
  2. Golden rule deck –SVRF (standard verification rule format ) given by TSMC foundry
  3. Run-set script – design detail ,golden deck detail chip or block
  4. Voltage info if the design is low power –

VDD ==0.95v

VDDH =1.3v

GND, VSS =0V

Calibre DRC flow

  1. Reads the GDs
  2. Passes the GDS
  3. Reads rule deck
  4. Verifies each rules
  5. Write the reports
  6. Save the DB

Output files

  1. Log files
  2. DRC Summery
  3. DRC_Error Maker
  4. SVDB (Std verification data base )

LVS

DRC Inputs :

  1. Full GDS/OAS
  2. Full spice /CDL
  3. Golden rule deck
  4. Run-set script
  5. HCELL list

Full spice generation

Flow

  1. Read the GDS/OAS File
  2. Checks if any missing cell definition
  3. Read the source spice
  4. Compare layout spice & source spice
  5. Write out the reports
  6. Save the DB for future Debugs

HCELL

ANDX1_RVT                                                       ANDX2_RVT

ANDX1_LVT                                                        ANDLVTX2

Use calibre RVE (result viewing Environmental)

 

ERC

Floating gate

Source & drain shorted

Nwell connection

Nets are Tie-High /Low

ANT

Metal  Hopping to higher layer

Insert antenna Diode

Add more gate area by adding dummy cells

Non Cummelative antenna check

Take the higher metal layer M4 is big

Only m4 consider

Cummelative antenna check

All the layer is conseder and give the report antenna

 

MMMC

Sign off corners

Sign off modes

Sta runs

Timing fixes

Dmsa

                Physical aware

                Logical aware

                Bottelneck analysis

                Manual fixes

 

Order of fixes

Clock DRV

Data DRV

Setup

Hold

Cross-talk

Manual fixes

DRV

                Max tra

                Max cap

                Max fan-out

Setup à different type of fixes

Hold à different type of fixes

Convention lithography àall the layers we can manufacture at time in conventional lithography 

16nm and bellow the geometry of the layers is much much closer here we are going to use the technique is called double pattern

Double pattern

First print one mask removes that mask and prints another mask 

The entire mask is same only

Convention lithography àall the layers in single time you get some shorts

We use the because of lithography limitations we cannot manufacture much   geometry  , shapes much that are  closer  with the help of double pattern we can manufacture much more closer with that help in terms of yield 

Colour Spacing Violations little trick for fixing this violations

DPTà

Colour spacing rules are applicable only on the DPT layers

16nmàm1,m2,m3

7nm àM0,M1,M2,M3

5nmà M0,M1,M2,M3,M4

DPT DRC Viol (M1,M2,M3)

  1. G0.1
  2. G.2

16nm FF

FFP ( 13+1 layers)

                FFC ( 11+1 layers)

16nm (Multi channel lib)

  1. P20 (HVT/RVT/LVT/ULVT)
  2. P16 (HVT/RVT/LVT/ULVT) 

28                                           16

Planner                                finfet

Single mask                        dpt

                                                Leakage less      

                                                Performance high

Disadvantages

  1. Manufacturing cost
  2. More IR drop Issues
    1. More switching because of more gates
    2. Consuming more power electrical energy is converted heating
    3. More PVT corners
  1. EM issues
  2. More cross-talk issues
    1. Spacing is less
  3.  

 

 

 

 

 

 

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