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Physical Design (PD)

  • Logic/Physical Synthesis, IO ring preparation & Bump Planning,Timing Constraints Preparation and Validation
  • Floorplan & power planning, Clock Tree Synthesis
  • Place and route, Low power implementation
  • Static Timing Analysis
  • Signal Integrity
  • IR drop Analysis and Repair
  • Physical Verification like DRC, LVS, Antenna, Density, ERC etc
  • Industry Standard EDA Tools:Synopsys, Cadence, Mentor

STA/Synthesis

  • Process Variation and related Margins
  • Peripheral Interface protocols and timing
  • Mission mode and Test mode Constraints (Data flow)
  • High Speed Clocking Architecture
  • Synchronous/Asynchronous designs
  • Signal Integrity
  • ECO implementation 
  • Sign-Off and Tapeout
  • Industry Standard EDA Tools: Synopsys, Cadence, Mentor

Physical Verification (PV)

  • Design Rule Check (DRC)
  • Base & Metal DRC
  • Layout versus Schematic (LVS)
  • LVS Flow, Input Requirements, checks, errors
  • Electrical Rule Check (ERC)
  • Lithography Process Checking
  • Antenna Checks
  • Latch-up
  • Reliability checks like EM and IR analysis
  • Double pattern checks
  • Design for manufacturability (DFM) checks
  • Electrostatic discharge (ESD) path checks

Analog Layout

  • Experts with experience down to 7nm process node
  • Floor planning, BUMP routing and Area optimization
  • Analog layout matching/shielding techniques
  • IR drop and EM analysis
  • ESD & clamps placement
  • Complex Mixed signal integration
  • Layout verification flows : DRC, LVS, Extraction, DFM, EM & IR

Design Verification (DV)

  • Understanding the design specification document and creating the test plan
  • Creating the complete verification environment using industry standard methodologies like UVM/OVM/VMM
  • Gate level simulations,Verification closure through corner case verification, coverage closure and regression closure
  • Advanced IP & SoC Verification, SV-UVM Based Constrained - Random Verification
  • Low Power Verification, Assertion based Verification, System verilog assertions
  • Palladium, Zebu & Veloce based Validation Silicon validation

RTL Design

  • Digital design: A solid understanding of digital logic, Boolean algebra, and sequential and combinational circuits is essential for RTL design.
  • Verilog and VHDL: These languages are typically used to write RTL models.
  • Problem-solving: Strong problem-solving skills help engineers identify issues, troubleshoot, and devise solutions.
  • Synthesis: Synthesis is the process of turning an abstract design into a chip that's correctly implemented in terms of logic gates.
  • Timing analysis: Timing analysis is critical for ensuring that the designed circuit meets performance specifications.
  • architectures: A solid foundation in these areas is important. HDLs: RTL design engineers need to master the syntax and semantics of HDLs.
  • RTL simulation, synthesis, and verification: RTL design engineers need to know the tools and methods for these tasks.
  • Architecture: A deep understanding of ARM Micro Architecture is helpful. Computer architecture and FPGA

Analog Design

  • CAD tools: Proficiency in CAD tools like SPICE simulators, layout tools, and scripting languages
  • Attention to detail: Analog circuits are sensitive to small variations Communication and collaboration:
  • The ability to work with cross-functional teams and explain technical concepts to stakeholders Analog and digital components: Knowledge of analog and digital components Circuit behaviors:
  • Understanding of circuit behaviors Problem-solving: The ability to solve problems
  • Consistency: The ability to maintain consistency Noise, sensitivity, gain, and bandwidth: Knowledge of noise, sensitivity, gain, and bandwidth Simulation skills:
  • The ability to use simulation skills to evaluate the reliability of analog systems Analog layout design: The ability to design analog layouts Device physics: Some knowledge of device physics

DFT

  • Digital Design and Semiconductor Technologies. In-Depth knowledge in terms of DFT Methodologies, such as scan-based testing ,
  • ATPG (Automatic Test Patter Generation )
  • BIST is also crucial.